Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together. The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation:

• Bulk MOS intrinsic models
• SOI/double-gate/multiple-gate/floating-gate MOS models
• Bipolar/HBT/SiGe/GaN/JFET models
• RF/noise/scalable capacitance/NQS models
• Statistical/predictive/process-based models
• Interconnection/passive device models
• Extrinsic/parasitic element models
• Reliability/hot carrier/tunneling/ESD models
• Atomic-level/quantum-mechanical compact models
• Numerical/TCAD/behavioral/table-based models
• Model parameter extraction and optimization
• Model-simulator interface and standardization

• Matthias Bucher, Technical University of Crete, Greece
• Robert Dutton, Stanford University, USA
• Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland
• Tor Fjeldly, Norwegian University of Science and Technology, Norway
• Jerry Fossum, University of Florida, USA
• Carlos Galup-Montoro, Universidade Federal de Santa Catarina, Brazil
• Gennady Gildenblat, Pennsylvania State University, USA
• John Hauser, North Carolina State University, USA
• Jin He, Peking University, China
• Chenming Hu and Mohan Dunga, University of California at Berkeley, USA
• Benjamín Iñíguez, Universitat Rovira i Virgili, Spain
• Dirk Klaassen, Philips Research Laboratories, The Netherlands
• Shiuh-Wuu Lee and Sivakumar Mudanai, Intel, USA
• Juin Liou, University of Central Florida, USA
• Ramana Malladi, IBM, USA
• Colin McAndrew, Freescale Semiconductor, USA
• Mitiko Miura-Mattausch and Tatsuya Ezaki, Hiroshima University, Japan
• Fabien Prégaldiny, InESS, France
• Chih-Tang Sah and Bin Jie, University of Florida, USA
• Michael Schröter, University of Technology Dresden, Germany
• Ehrenfried Seebacher, Austriamicrosystems AG, Austria
• Michael Shur, Rensselaer Polytechnic Institute, USA
• Josef Watts, IBM, USA
• Man Wong, Hong Kong University of Science and Technology, Hong Kong
• Yuan Taur, University of California at San Diego, USA
• Xing Zhou, Nanyang Technological University, Singapore

There are 27 invited papers, which are categorized in the following topic areas:

Bulk MOS intrinsic models

• Carrier Generation and Recombination Currents At Interface Traps In Long-Channel Surface-Potential-Based MOS Transistor Compact

Chih-Tang Sah, University of Florida, US
• Recent Advances in the EKV3.0 MOSFET Model

Matthias Bucher, Technical University of Crete, GR
• Symbolic Charge-based MOSFET Model

Carlos Galup-Montoro, Universidade Federal de Santa Catarina, BR
• Theory and Modeling Techniques Used in PSP Model

Gennady Gildenblat, Pennsylvania State University, US
• An MOS Model with an Improved Mobility Model

John Hauser, North Carolina State University, US
• Benchmark Tests on Conventional Surface Potential Based Charge-Sheet Models and PUNSIM Development

Jin He, Peking University, CN
• Accuracy of Long-Channel Surface-Potential-Based MOS Transistor Compact Models

Bin Jie, University of Florida, US
• Advanced Compact MOSFET Model HiSIM2 Based Surface Potentials with a Minimum Number of Approximations

Mitiko Miura-Mattausch, Hiroshima University, JP
• Halo Doping: Physical Effects and Compact Modeling

Sivakumar Mudanai, Intel, US
• Compact Iterative Field Effect Transistor Model

Michael Shur, Rensselaer Polytechnic Institute, US
• Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling

Xing Zhou, Nanyang Technological University, SG

• BSIM4 and BSIM Multi-Gate Progress

Mohan Dunga, University of California at Berkeley, US
• A Charge-Based Compact Model of Double Gate MOSFET

Christian Enz, Swiss Center for Electronics and Microtechnology, CH
• Precise 2D Compact Modeling of Nanoscale DG MOSFETs Based on Conformal Mapping Techniques

Tor Fjeldly, Norwegian University of Science and Technology, NO
• Recent Upgrades and Applications of UFDG

Jerry Fossum, University of Florida, US
• DC to RF Small-Signal Compact DG MOSFET Model

Benjamín Iñíguez, Universitat Rovira i Virgili, ES
• An Explicit Quasi-static Charge-based Compact Model for Symmetric DG MOSFET

Fabien Prégaldiny, InESS, FR
• On the Modeling of the Current-Voltage Characteristics of a Symmetrical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with an Undoped Body

Man Wong, Hong Kong University of Science and Technology, HK
• Compact Modeling of Short-channel Double-gate MOSFETs

Yuan Taur, University of California at San Diego, US

• Device Correlation: Modeling using Uncorrelated Parameters, Characterization Using Ratios and Differences

Colin McAndrew, Freescale Semiconductor, US
• Modeling Small MOSFETs Using Ensemble Devices

Josef Watts, IBM, US

• Effects of Scaling on Modeling of Analog RF MOS Devices

Robert Dutton, Stanford University, US

• High-Voltage LDMOS Compact Modeling

Dirk Klaassen, Philips Research Laboratories, NE
• Analog Compact Modeling for a 20-120V HV CMOS Technology

Ehrenfried Seebacher, Austriamicrosystems AG, AT

• Compact Modeling of Spiral Inductors for RF Applications

Juin Liou, University of Central Florida, US

• Development and Design Kit Integration of a Scalable and Statistical High Current Model for Advanced SiGe HBTs

Ramana Malladi, IBM, US
• Charge-storage Calculation for Si-based Bipolar Transistors from Device Simulation

Michael Schröter, University of Technology Dresden, DE

For the accepted poster papers, the deadline for the final 4-page manuscript is 24 Feb. 2006.
See Nanotech website for instructions for authors:

There are 36 contributed poster papers, which are listed below (speakers underlined).

• Improved Basic Symmetry Tests for MOSFET Models

C. McAndrew, Freescale Semiconductor, US
• Scalable MOSFET Short-channel Charge Model in All Regions

G.H. See, S.B. Chiah, X. Zhou, K. Chandrasekaran, W. Shangguan, Z. Zhu, G.H. Lim, S.M. Pandey, M. Cheng, S. Chu, and L-C Hsia, Nanyang Technological University, SG
• Compact Modeling of Nonlinearities in Submicron MOSFETs

P.D. da Silva, F.R. de Sousa, C.G. Montoro and M.C. Schneider, Federal University of Santa Catarina, BR
• Charge-Based Formulation of Thermal Noise in Short-Channel MOS Transistors

V.C. Paim, C. Galup-Montoro and M.C. Schneider, Federal University of Santa Catarina, BR
• On the Compact Modelling of Induced Gate Noise in the MOS Transistor

A.S. Roy and C.C. ENz, Swiss Federal Institute of Technology, Lausanne (EPFL), CH
• Low-Frequency and RF Performance of Schottky-Diode for RFIC Applications and the Observation of RTS Noise Characteristics

Y.Z. Xiong, G.Q. Lo, J.L. Shi, M.B. Yu, W.Y. Loh and D.L. Kwong, Institute of Microelectronics, SG
• Two-Tone Distortion Modeling for SiGe HBTs Using the High-Current Model

R. Malladi, V. Borich, S.L. Sweeney, J. Rascoe, K.M. Newton, S. Venkatadri, J. Yang and S. Chen, IBM Systems and Technology, US
• BSIM Model for MOSFET Flicker Noise Statistics: Technology Scaling, Area, and Bias Dependence

M. Erturk, R. Anna, J.C. Lee, L.H. Pan, J.R. Jones, K.M. Newton, T. Xia and C.J. LaMothe, IBM Systems and Technology, US
• Investigation of Substrate Current Effects and Modeling of Substrate Resistance Network for RFCMOS

J.C. Lee, R.B. Anna, L.H. Pan and K.M. Newton, IBM Systems and Technology, US
• NQS Effects in MOSFET's and its Implementation in Advanced Compact Models

Y. Ma, M-C Jeng and Z. Liu, Cadence Design Systems, US
• Capacitance Modeling for LDMOS

Y. Ma, P. Chen, M-C Jeng and Z. Liu, Cadence Design Systems, US
• TCAD-based Process Dependant HSPICE Model Parameter Extraction

Y. Mahotin and S. Tirumala, Synopsys, US
• A Carrier Based Analytic Model for Undoped Surrounding-Gate MOSFETs

J. He, Z. Xing, G. Zhang and Y. Wang, Peking University, CN
• Compact Modeling of Doped Symmetric DG MOSFETs with Regional Approach

Z.M. Zhu, K. Chandrasekaran, X. Zhou, W. Shangguan, G.H. See, S.B. Chiah, S.C. Rustagi and N. Singh, Nanyang Technological University, SG
• Explicit Compact Model of Independent Double Gate MOSFET

M. Reyboz, O. Rozeau, T. Poiroux, P. Martin and J. Jomaah, CEA, FR
• Capacitance Model for Four-Terminal DG MOSFETs

T. Nakagawa, T. Sekigawa, T. Tsutsumi, M. Hioki, S. O’uchi and H. Koike, National Institute of Advanced Industrial Science and Technology, JP
• A Computationally Efficient Method for Analytical Calculation of Potentials in Undoped Symmetric DG SOI MOSFET

O. Cobianu and M. Glesner, Darmstadt University of Technology, DE
• Compact Model of Drain-Current in Double-Gate MOSFETs Including Carrier Quantization and Short-channel Effects

X. Loussier, D. Munteanu, J.L. Autran, S. Harrison and R. Cerutti, L2MP, FR
• Performance Analysis of Double-Gate MOSFET-based Circuits Using a Compact Model Implemented in Eldo IC Analog Simulator

O. Tintori, X. Loussier, D. Munteanu, J.L. Autran, A. Regnier and R. Bouchakour, L2MP, FR
• Polysilicon Gate Depletion Effect for Fabricated Double-Gate MOSFETs

T. Tsutsumi, Y. Liu, T. Nakagawa, T. Sekigawa, S. O’uchi, M. Hioki, E. Suzuki and H. Koike, National Institute of Advanced Industrial Science and Technology, JP
• Comparison of Three Region Multiple Gate Nanoscale Structures for Reduced Short Channel Effects and High Device Reliability

K. Goel, M. Saxena, M. Gupta and R.S. Gupta, University of Delhi South Campus, IN
• Compact Model for Short Channel Effects in Source/Drain Engineered Nanoscale Double Gate (DG) SOI MOSFETs

A. Kranti and G.A. Armstrong, Queen's University of Belfast, UK
• Compact Models for Double Gate and Surrounding Gate MOSFETs

H. Abebe, E. Cumberbatch, H. Morris and S. Uno, San Jose State University, US
• SOI CMOS Compact Modeling Based on TCAD Device Simulations

A. Botula, S. Furkay, D.C. Sheridan, J.M. Johnson and M-H Na, IBM Corporation, US
• On Idlow with Emphasis on Speculative SPICE Modeling

Q. Chen, Z-Y Wu, A.B. Icel, J-S Goo, S. Krishnan, C. Thuruthiyil, N. Subba, S. Suryagandh, J.X. An, T. Ly, M. Radwin, J. Yonemura and F. Assad, Advanced Micro Devices, US
• Dynamic Behavior Model for High-K MOSFETs

M.V. Dunga, X. Xi, A.M. Niknejad and C. Hu, University of California, Berkeley, US
• A Simple Yet Accurate Mismatch Model for Circuit simulation

Z. Jin, Y-M Lee, J. Watts, A. Bonaccio, G. Schroer and N. Pai, IBM, US
• Enhanced Junction Depletion Capacitance Modeling

F.G. Anderson, R.M. Rassel and M.A. Lavoie, IBM Microelectronics, US
• A Compact Model of Ballistic CNFET for Circuit Simulation

B.C. Paul, S. Fujita, M. Okajima and T. Lee, Toshiba America Research, JP
• A Circuit-Compatible Model of Ballistic Silicon Nanowire Transistors

J. Chen, Agere Systems, US
• Compact Modeling of Threshold Voltage in Nanoscale Strained-Si/SiGe MOSFETs

S. Nawal, V. Venkataraman and M.J. Kumar, Indian Institute of Technology, New Delhi, IN
• Compact Model Methodology for Dual-Stress Nitride Liner Films in a 90nm SOI ULSI Technology

R.Q. Williams, D. Chidambarrao, J.H. McCullen, S. Narasimha, T.G. Mitchell and D. Onsongo, IBM Corporation, US
• A Transient Lumped Element Model for a Phase Change Circuit Memory Element

H.G.A. Huizing, D. Tio Castro, J.C.J. Paasschens and M.H.R. Lankhorst, Philips, NL
• Static Analog Design Methodology

F. Guigues, F. Rudolff and E. Kussener, L2MP UMR 6137 CNRS - ISEN-Toulon, FR
• Interrelations Between Threshold Voltage Definitions and Extraction Methods

M.C. Schneider, C. Galup-Montoro, M.B. Machado and A.I.A. Cunha, Federal University of Santa Catarina, BR
• A Unified Parameter Extraction Procedure for Scalable Bipolar Transistor Model Mextram

H-C Wu, S. Mijalkovic and J.N. Burghartz, Delft University of Technology, NL